Stimulus-response tests include a wide variety of tests which may be used to evaluate, inter alia, cognitive and neurobehavioural performance of human and other animal subjects. Non-limiting examples of stimulus-response tests include: psychomotor vigilance task (PVT) tests, digit symbol substitution task (DSST) tests, stroop tests and/or the like.
In general, stimulus-response tests involve providing stimulus to a subject (e.g. a human or other animal subject) and observing the resultant response. Observed responses may then be further analyzed. Analysis of results from stimulus-response tests may include generating metrics indicative of the type of response (e.g. for a given stimulus event) and/or the timing of the response (e.g. relative to the timing of a stimulus event). It will be appreciated that for stimulus-response tests, where the timing of the response relative to the stimulus is considered to be important, measurement of the timing of stimulus and response events may be of commensurate importance.
In many cases, stimulus-response tests are conducted using a general purpose computer which may be outfitted with a suitable stimulus output device and a suitable response input device. FIG. 1 is a schematic block diagram illustration of a particular exemplary stimulus-response test delivery system 100 implemented on a general purpose computer 102 wherein the test is being administered on a subject 104. In addition to computer 102, test delivery system 100 incorporates a stimulus output device 106 for providing a stimulus output 108 to subject 104 and a response input device 119 for receiving a response 112 from subject 104. Stimulus output device 106 may comprise a well known computer output device (e.g. a monitor, speakers or the like) or may comprise a specialized output device (e.g. digitally controlled light source or the like) for the purpose of implementing a particular stimulus-response test. Similarly, response input device 110 may comprise a well known computer input device (e.g. a mouse, a keyboard, a touch screen, a graphics tablet or the like) or a specialized input device (e.g. a button, a digital audio input device (e.g. microphone), a still camera, a video camera, a force-feedback device or the like).
Computer 102 includes a controller 114 (e.g. a CPU or the like). Controller 102 typically has access to a hard drive 116 and/or other memory (e.g. RAM memory) 118, which houses a number of software applications 120A . . . 120i (collectively, software applications 120) or suitable portions of such software applications 120. Typically, software applications 120 will reside at least in part on hard drive 116 and may be loaded into memory 118 in whole or in part, as and when required by controller 114. As is known, controller 114 may multi-task in order to run a relatively large number of software applications 120 at the same time. One or more of software applications 120 may include the software application(s) associated with the administration of the stimulus-response test. Other software applications 120 may include, by way of non-limiting example, the operating system associated with computer 102, drivers associated with I/O interfaces 130 and I/O devices 132, any other programs which a test administrator may be running on computer 102 and/or the like.
Computer 102 also typically includes a stimulus output interface 122 which sends appropriate output signals 124 to stimulus output device 106 under the direction of controller 114 (e.g. via signal 115). By way of non-limiting example, stimulus output interface 122 can comprise any I/O interface common to computers, such as a USB port, a serial port, a parallel port, a network port (e.g. a wireless network port, an ethernet port), a IEEE 1394 interface (e.g. FireWire™) port or the like. Stimulus output interface 122 may be physically connected to deliver signal 124 to stimulus output device 106 or wirelessly connected to deliver signal 124 to stimulus output device 106. Computer 102 also typically includes a response input interface 126 which receives response signal 128 from response input device 110 and relays this information to controller 114 (e.g. via test-system response signal 127). Response input interface 126 may comprise any of the non-limiting exemplary interfaces described above for stimulus output interface 122. Response input interface 126 may be physically connected to receive response signal 128 from response input device 110 or wirelessly connected to receive response signal 128 from response input device 110. In addition to stimulus output interface 122 and response input interface 126, computer 102 may include other I/O interfaces 130 which interface with other I/O devices 132 under the direction of controller 114.
In operation, controller 114 runs one or more software applications 120 associated with the administration of the stimulus-response test and outputs a suitable signal 115 which causes stimulus output interface 122 to output signal 124 and stimulus output device 106 to output a stimulus event 108. When subject 104 perceives stimulus event 108 to be of the type for which a response is desired, subject 104 responds 112 using response input device 110 which generates a response signal 128 at response input interface 126 which is then directed to controller 114 as test-system response signal 127. An issue, particularly when the timing of response 112 relative to stimulus event 108 is of interest is the latency associated with computer 102, the latency of the response input device 110, the latency of the stimulus output device 106, and the latency of the interfaces between these components (e.g. response input interface 126 and stimulus output interface 122). By way of non-limiting example, computer 102 may exhibit latency because of processing delays (e.g. processor 114 is busy performing the processing associated with one or more of software applications 120), because of delays associated with the interfacing between controller 114 and memory 118, between controller 114 and hard drive 116 and/or between hard drive 116 and memory 118, because of delays associated with interfacing between I/O interfaces 122, 126, 130 and/or I/O devices 106, 110, 132 and/or the like. By way of non-limiting example, stimulus output device 106 may exhibit latency between receiving an output signal 124 and transmitting stimulus 108 due to processing delays associated with stimulus output device 106, mechanical delays (e.g. switch turning on), optical displays transitioning between on and off states (e.g. pixels on an LCD monitor) and/or the like. By way of non-limiting example response input device 110 may exhibit latency between receiving response 112 and transmitting response signal 128 due to processing delays in the response input device 110, mechanical delays (e.g. travel time of a button before electrical connection is made), electrical delays (e.g. debouncing circuits, or time for signal to cross a detection threshold) and/or the like. Such latencies can easily be on the order of magnitude of the stimulus-response timing for which a measurement is desired.
There is a general desire to provide systems and methods for calibrating a stimulus-response test delivery system to account for such latency. Such calibration may permit the timing metrics associated with stimulus-response tests to be determined with increased accuracy and/or precision and/or may provide more information about the certainty/confidence associated with stimulus-response test results.
It can be desirable to implement test delivery system 100 with a wide variety of computers 102 (or other hardware systems), stimulus output devices 106 and/or response input devices 110. Such computers 102 may be running a wide variety of software processes. Each such test delivery system 100 may exhibit different latencies. Accordingly, there is a desire to provide systems and methods for calibrating a stimulus-response test delivery system to account for such different latencies. Such calibration may permit stimulus-response results to be accurate, repeatable and/or comparable as between different testing systems.